Low-Level Code Agent

What we offer

We are building an MLIR-based compiler for a new non–von Neumann architecture, unlocking massive parallelism and efficiency. Our work sits at the frontier of compilers, architectures, and AI-driven code generation. Engineers here work hands-on with new chips, from primitives to ML frameworks. Researchers tackle fundamental questions in autonomous code generation and optimization. Together, we design the software stack that will make tomorrow’s hardware usable.

About us

OUR EDGE

What will you do

E / 1

Build the compiler layer: integrate a new non–von Neumann accelerator into ML frameworks like PyTorch and TensorFlow using MLIR.

E / 1

Build the compiler layer: integrate a new non–von Neumann accelerator into ML frameworks like PyTorch and TensorFlow using MLIR.

E / 2

Bridge high-level ML to low-level compute: transform model graphs into optimized kernels and collaborate with low-level engineers on core operations.

E / 2

Bridge high-level ML to low-level compute: transform model graphs into optimized kernels and collaborate with low-level engineers on core operations.

E / 3

Work close to the metal: dive into C++ libraries and hardware APIs to configure cores, control execution, and fine-tune data flows.

E / 3

Work close to the metal: dive into C++ libraries and hardware APIs to configure cores, control execution, and fine-tune data flows.

E / 4

Explore AI for code: research LLM-based agents that can generate and optimize low-level code for novel architectures.

E / 4

Explore AI for code: research LLM-based agents that can generate and optimize low-level code for novel architectures.

Join the team your way

OUR EDGE

What you will do

E / 1

Conduct cutting-edge research on time-series foundation models, reinforcement learning agents, or multimodal LLM architectures in financial domains.

E / 2

We offer full access to essential datasets, high-performance compute, and research-to-execution stack.

E / 3

Collaborate with CertEq’s core engineering and research teams.

E / 4

Potentially convert your work into internal tools, publishable research, or production-grade modules.

For seasoned engineers

Senior engineer

Hands-on experience with a novel compute architecture

Work with top-tier hardware architects

Competitive compensation

Requirements

Strong C/C++ and performance optimization skills

Low-level programming on GPUs/TPUs/DSPs/FPGA (CUDA, OpenCL, SYCL)

Experience with LLVM/MLIR and compiler backends

Understanding of ML models and core ops (matmul, conv, etc.)

Integration of PyTorch/TensorFlow models to custom hardware

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For experienced researchers

Senior researcher

Publishable research

Direct mentorship from CSO

Competitive compensation

Requirements

Background in hardware-software co-design and accelerator/architecture research

Experience with generative AI for code and automated code optimization

Knowledge of ML frameworks and workload integration (PyTorch, TensorFlow, JAX)

Compiler expertise (LLVM/MLIR, graph compilers, optimizations) as a plus

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Chief of Science

Irina Rish

Irina Rish is a Full Professor at the Université de Montréal (UdeM), where she leads the Autonomous AI Lab, and is a core faculty member of MILA - Quebec AI Institute. She holds a Canada Excellence Research Chair (CERC) and a CIFAR Chair. Irina completed her MSc and PhD in AI at the University of California, Irvine, and holds an MSc in Applied Mathematics from Moscow Gubkin Institute.

About Irina

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